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?2001 silicon storage technology, inc. s71181-03-000 9/01 384 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. flashflex, in-application programming, iap, and softlock are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications features: ? 8-bit 8051 family compatible microcontroller (mcu) with embedded superflash memory sst89e564/sst89e554 is 5v operation ? 0 to 40 mhz operation at 5v sst89v564/sst89v554 is 3v operation ? 0 to 25 mhz operation at 3v fully software and development toolset compatible as well as pin-for-pin package compatible with standard 8xc5x microcontrollers 1 kbyte register/data ram dual block superflash eeprom ? sst89e564/sst89v564: 64 kbyte primary block + 8 kbyte secondary block (128-byte sector size) ? sst89e554/sst89v554: 32 kbyte primary block + 8 kbyte secondary block (128-byte sector size) ? individual block security lock ? concurrent operation during in-application programming (iap) ? block address re-mapping support external address range up to 64 kbyte of program and data memory three high-current drive pins (16 ma each) three 16-bit timers/counters full-duplex enhanced uart ? framing error detection ? automatic address recognition eight interrupt sources at 4 priority levels watchdog timer (wdt) four 8-bit i/o ports (32 i/o pins) second dptr register reduce emi mode (inhibit ale through auxr sfr) spi serial interface ttl- and cmos-compatible logic levels brown-out detection extended power-saving modes ? idle mode ? power down mode with external interrupt wake-up ? standby (stop clock) mode pdip-40, plcc-44 and tqfp-44 packages temperature ranges: ? commercial (0c to +70c) ? industrial (-40c to +85c) product description sst89e564, sst89v564, sst89e554, and sst89v554 are members of the flashflex51 family of 8-bit microcontrol- lers. the flashflex51 is a family of microcontroller products designed and manufactured on the state-of-the-art super- flash cmos semiconductor process technology. the device uses the same powerful instruction set and is pin-for- pin compatible with standard 8xc5x microcontroller devices. the device comes with 72/40 kbyte of on-chip flash eeprom program memory using sst?s patented and pro- prietary cmos superflash eeprom technology with the sst?s field-enhancing, tunneling injector, split-gate mem- ory cells. the superflash memory is partitioned into 2 independent program memory blocks. the primary super- flash block 0 occupies 64/32 kbyte of internal program memory space and the secondary superflash block 1 occupies 8 kbyte of internal program memory space. the 8-kbyte secondary superflash block can be mapped to the lowest location of the 64/32 kbyte address space; it can also be hidden from the program counter and used as an independent eeprom-like data memory. the flash memory blocks can be programmed via a standard 87c5x otp eprom programmer fitted with a special adapter and firmware for sst?s device. during the power-on reset, the device can be configured as a slave to an external host for source code storage or as a master to an external host for in-application programming (iap) operation. the device is designed to be programmed ?in-system? and ?in-applica- tion? on the printed circuit board for maximum flexibility. the device is pre-programmed with an example of bootstrap loader in the memory, demonstrating the initial user pro- gram code loading or subsequent user code updating via the ?iap? operation. an example of bootstrap loader is for the user?s reference and convenience only. sst does not guarantee the functionality or the usefulness of the sample bootstrap loader. chip-erase or block-erase operations will erase the pre-programmed sample code. in addition to 72/40 kbyte of superflash eeprom pro- gram memory on-chip, the device can address up to 64 kbyte of external program memory. in addition to 1024 x 8 bits of on-chip ram, up to 64 kbyte of external ram can be addressed. sst?s highly reliable, patented superflash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash eeproms. these advantages translate into significant cost and reliability benefits for our customers. flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 sst89e/v564 sst89e/ve554 flashflex51 mcu
2 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table of contents product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 program memory block switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.1 reset configuration of program memory block switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 special function registers (sfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.0 flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 external host programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.2 arming command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.3 detail explanation of the external host mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.4 external host mode clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1.5 flash operation status detection via external host handshake . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1.6 step-by-step instructions to perform external host mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1.7 flash memory programming timing diagrams with external host mode . . . . . . . . . . . . . . . . . . 28 4.2 in-application programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.1 in-application programming mode clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.2 memory bank selection for in-application programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.3 iap enable bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.4 in-application programming mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.5 polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.6 interrupt termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.0 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.0 serial i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 enhanced universal aysnchronous receiver/transmitter (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 framing error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 automatic address recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 3 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 7.0 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.0 security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 hard lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2 softlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 security lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3 brown-out detection reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.4 interrupt priority and polling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.5 power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.2 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.3 standby mode (stop clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.6 clock input options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.7 recommended capacitor values for crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.0 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 absolute maximum stress ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 operation range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.0 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.0 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 list of figures figure 2-1: pin assignments for 40-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2-2: pin assignments for 44-lead tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2-3: pin assignments for 44-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3-1: program memory organization for sst89e564 and sst89v564 . . . . . . . . . . . . . . . . . . . . . 10 figure 3-2: program memory organization for sst89e554 and sst89v554 . . . . . . . . . . . . . . . . . . . . . 11 figure 4-1: i/o pin assignments for external host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 4-2: read-id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4-3: select-block1 / select-block0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4-4: chip-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 4-5: block-erase for sst89e564/sst89v564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 4-6: block-erase for sst89e554/sst89v554 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 4-7: sector-erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 4-8: byte-program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 4-9: prog-sb1 / prog-sb2 / prog-sb3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 4-10: prog-sc0 / prog-sc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 4-11: byte-verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6-1: spi master-slave interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6-2: spi transfer format with cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6-3: spi transfer format with cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 7-1: block diagram of programmable watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 8-1: security lock levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 9-1: power-on reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9-2: oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 10-1: i dd test condition, active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 10-2: i dd test condition, idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 10-3: i dd test condition, power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 10-4: i dd test condition, standby (stop clock) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 10-5: ac testing input/output, float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 10-6: external program memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 figure 10-7: external data memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 10-8: external data memory write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10-9: external clock drive waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10-10: shift register mode timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 5 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 list of tables table 2-1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3-1: sfcf values for program memory block switching for sst89e564/sst89v564 . . . . . . . . 11 table 3-2: sfcf values for program memory block switching for sst89e554/sst89v554 . . . . . . . . 12 table 3-3: sfcf values under different reset conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3-4: flashflex51 sfr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3-5: cpu related sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-6: flash memory programming sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-7: watchdog timer sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-8: timer/counters sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-9: interface sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4-1: external host mode commands for sst89e564/sst89v564. . . . . . . . . . . . . . . . . . . . . . . . 24 table 4-2: external host mode commands for sst89e554/sst89v554. . . . . . . . . . . . . . . . . . . . . . . . 25 table 4-3: signature bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4-4: iap address resolution for sst89e564/sst89v564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 4-5: in-application programming mode commands for sst89e564/sst89v564 . . . . . . . . . . . . 35 table 4-6: in-application programming mode commands for sst89e554/sst89v554 . . . . . . . . . . . . 35 table 4-7: flash memory programming/verification parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8-1: security lock options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8-2: security lock access table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 9-1: interrupt polling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 9-2: power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 10-1: operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 10-2: reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 10-3: dc electrical characteristics: 40mhz devices; 4.5-5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10-4: dc electrical characteristics: 25mhz devices; 2.7-3.6v . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 10-5: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 10-6: external clock drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 10-7: serial port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 1.0 functional blocks 8 interrupts superflash eeprom primary block 32k/64k x8 1 secondary block 8k x8 i/o i/o i/o i/o watchdog timer interrupt control 8051 cpu core ram 1k x8 security lock i/o port 0 i/o port 1 i/o port 2 i/o port 3 8-bit enhanced uart spi timer 0 (16-bits) timer 1 (16-bits) timer 2 (16-bits) 8 8 8 8 384 ill b1.4 1. 64k x8 for sst89e564 and sst89v564 32k x8 for sst89e554 and sst89v554 f unctional b lock d iagram
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 7 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 2.0 pin assignments figure 2-1: p in a ssignments for 40- pin pdip figure 2-2: p in a ssignments for 44- lead tqfp figure 2-3: p in a ssignments for 44- lead plcc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (t2) p1.0 (t2 ex) p1.1 p1.2 p1.3 (ss#) p1.4 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 40-pin pdip top view 384 ill f18.3 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 reserved (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# reserved ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 (ss#) p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) reserved v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss reserved (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 384 ill f19.5 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 44-lead tqfp top view 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 reserved (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# reserved ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 p1.4 (ss#) p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) reserved v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss reserved (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 44-lead plcc top view 384 ill f20.4
8 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 2.1 pin descriptions table 2-1: p in d escriptions (1 of 2) symbol type 1 name and functions p0[7:0] i/o port 0: port 0 is an 8-bit open drain bi-directional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins float that have ?1?s written to them, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external memory. in this application, it uses strong internal pull- ups when transitioning to v oh . port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. external pull-ups are required during program verification. p1[7:0] i/o with internal pull-ups port 1: port 1 is an 8-bit bi-directional i/o port with internal pull-ups. the port 1 output buffers can drive ls ttl inputs. port 1 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 1 pins that are exter- nally pulled low will source current (i il , see tables 10-3 and 10-4) because of the internal pull- ups. p1[5, 6, 7] have high current drive of 16 ma. port 1 also receives the low-order address bytes during the external host mode programming and verification. p1[0] i/o t2: external count input to timer/counter 2 or clock-out from timer/counter 2 p1[1] i t2ex: timer/counter 2 capture/reload trigger and direction control p1[4] i/o ss#: master input or slave output for spi p1[5] i/o mosi: master output line, slave input line for spi p1[6] i/o miso: master input line, slave output line for spi p1[7] i/o sck: master clock output, slave clock input line for spi p2[7:0] i/o with internal pull-ups port 2: port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 2 pins that are externally pulled low will source current (i il , see tables 10-3 and 10-4) because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (movx@dptr). in this application, it uses strong internal pull-ups when transitioning to v oh . port 2 also receives some control signals and a partial of high- order address bits during the external host mode programming and verification. p3[7:0] i/o with internal pull-ups port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. the port 3 output buffers can drive ls ttl inputs. port 3 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 3 pins that are exter- nally pulled low will source current (i il , see tables 10-3 and 10-4) because of the internal pull- ups. port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. p3[0] i rxd: serial input line p3[1] o txd: serial output line p3[2] i int0#: external interrupt 0 input p3[3] i int1#: external interrupt 1 input p3[4] i t0: external count input to timer/counter 0 p3[5] i t1: external count input to timer/counter 1 p3[6] o wr#: external data memory write strobe p3[7] o rd#: external data memory read strobe psen# i/o program store enable: psen# is the read strobe to external program store. when the device is executing from internal program memory, psen# is inactive (v oh ). when the device is executing code from external program memory, psen# is activated twice each machine cycle, except when access to external data memory while one psen# activation is skipped in each machine cycle. a forced high-to-low input transition on the psen# pin while the rst input is continually held high for more than ten machine cycles will cause the device to enter external host mode for programming.
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 9 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 rst i reset: while the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. after a reset, if the psen# pin is driven by a high-to-low input transition while the rst input pin is held high, the device will enter the external host mode, otherwise the device will enter the normal operation mode. ea# i external access enable: ea# must be driven to v il in order to enable the device to fetch code from the external program memory. ea# must be driven to v ih for internal program exe- cution. however, security lock level 4 will disable ea#, and program execution is only possi- ble from internal program memory. the ea# pin can tolerate a high voltage 2 of 12v (see ?absolute maximum stress ratings? on page 47). ale/prog# i/o address latch enable: ale is the output signal for latching the low byte of the address dur- ing accesses to external memory. this pin is also the programming pulse input (prog#) for the external host mode. ale is activated twice each machine cycle, except when access to external data memory, one ale activation is skipped in the second machine cycle. however, if ao is set to 1, ale is disabled. (see ?auxiliary register (auxr)? on page 20) xtal1 xtal2 i o oscillator: input and output to the inverting oscillator amplifier. xtal1 is input to internal clock generation circuits from an external clock source. v dd i power supply: supply voltage during normal, idle, power down, and standby mode opera- tions. vss i ground: circuit ground. (0v reference) t2-1.6 384 1. i = input; o = output 2. it is not necessary to receive a 12v programming supply voltage during flash programming. table 2-1: p in d escriptions (c ontinued ) (2 of 2) symbol type 1 name and functions
10 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 3.0 memory organization the device has separate address spaces for program and data memory. 3.1 program memory there are two internal flash memory blocks in the device. the primary flash memory block (block 0) has 64/32 kbyte. the secondary flash memory block (block 1) has 8 kbyte. since the total program address space is limited to 64/32 kbyte, the sfcf[1:0] bit are used to control program bank selection. please refer to figure 3-1 and figure 3-2 for the program memory configurations. program bank select is described in the next section. the 64k/32k x8 primary superflash block is organized as 512/256 sectors, each sector consists of 128 bytes. the 8k x8 secondary superflash block is organized as 64 sectors, each sector consists also of 128 bytes. for both blocks, the 7 least significant program address bits select the byte within the sector. the remainder of the pro- gram address bits select the sector within the block. figure 3-1: p rogram m emory o rganization for sst89e564 and sst89v564 384 ill f48.5 external 64 kbyte ea# = 0 ffffh 0000h 64 kbyte block 0 ea# = 1 sfcf[1:0] = 01, 10, 11 ffffh 0000h 56 kbyte block 0 8 kbyte block 1 ea# = 1 sfcf[1:0] = 00 ffffh 2000h 0000h 1fffh
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 11 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 3-2: p rogram m emory o rganization for sst89e554 and sst89v554 3.2 program memory block switching the program memory block switching feature of the device allows either block 1 or the lowest 8 kbyte of block 0 to be used for the lowest 8 kbyte of the program address space. sfcf[1:0] controls program memory block switching. 384 ill f48b.3 external 64 kbyte ea# = 0 ffffh 0000h 32 kbyte block 0 ea# = 1 sfcf[1:0] = 10, 11 ffffh 0000h 24 kbyte block 0 8 kbyte block 1 8 kbyte block 1 ea# = 1 sfcf[1:0] = 00 ffffh 2000h 7fffh 8000h dfffh e000h dfffh e000h 7fffh 8000h 0000h 1fffh external 24 kbyte 8 kbyte block 1 external 24 kbyte external 32 kbyte ea# = 1 sfcf[1:0] = 01 ffffh 7fffh 8000h 0000h 32 kbyte block 0 table 3-1: sfcf v alues for p rogram m emory b lock s witching for sst89e564/sst89v564 sfcf[1:0] program memory block switching 01, 10, 11 block 1 is not visible to the pc; block 1 is reachable only via in-application programming from 000h - 1fffh. 00 block 1 is overlaid onto the low 8k of the program address space; occupying address locations 0000h - 1fffh. when the pc falls within 0000h - 1fffh, the instruction will be fetched from block 1 instead of block 0. outside of 0000h - 1fffh, block 0 is used. locations 0000h - 1fffh of block 0 are reachable through in-application programming. t3-1.0 384
12 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 3.2.1 reset configuration of program memory block switching program memory block switching is initialized after reset according to the state of the start-up configuration bit sc0. the sc0 bit is programmed via an external host mode command or an iap mode command. see table 4-2 and table 4-6. once out of reset, the sfcf[0] bit can be changed dynam- ically by the program for desired effects. changing sfcf[0] will not change the sc0 bit. caution must be taken when dynamically changing the sfcf[0] bit. since this will cause different physical memory to be mapped to the logical program address space. the user must avoid executing block switching instructions within the address range 0000h to 1fffh. 3.3 data memory the device has 1024 x 8 bits of on-chip ram and can address up to 64 kbyte of external data memory. the device has four sections of internal data memory: 1. the lower 128 bytes of ram (00h to 7fh) are directly and indirectly addressable. 2. the higher 128 bytes of ram (80h to ffh) are indirectly addressable. 3. the special function registers (sfrs, 80h to ffh) are directly addressable only. 4. the expanded ram of 768 bytes (00h to 2ffh) is indirectly addressable by the move external instruction (movx) and clearing the extram bit. (see ?auxiliary register (auxr)? on page 20) 3.4 dual data pointers the device has two 16-bit data pointers. the dptr select (dps) bit in auxr1 determines which of the two data pointers is accessed. when dps=0, dptr0 is selected; when dps=1, dptr1 is selected. quickly switching between the two data pointers can be accomplished by a single inc instruction on auxr1. 3.5 special function registers (sfr) most of the unique features of the flashflex51 microcon- troller family are controlled by bits in special function regis- ters (sfrs) located in the sfr memory map shown in table 3-4. individual descriptions of each sfr are provided and reset values indicated in tables 3-5 to 3-9. table 3-2: sfcf v alues for p rogram m emory b lock s witching for sst89e554/sst89v554 sfcf[1:0] program memory block switching 10, 11 block 1 is not visible to the pc; block 1 is reachable only via in-application programming from e000h - ffffh. 01 both block 0 and block 1 are visible to the pc. block 0 is occupied from 0000h - 7fffh. block 1 is occupied from e000h - ffffh. 00 block 1 is overlaid onto the low 8k of the program address space; occupying address locations 0000h - 1fffh. when the pc falls within 0000h - 1fffh, the instruction will be fetched from block 1 instead of block 0. outside of 0000h - 1fffh, block 0 is used. locations 0000h - 1fffh of block 0 are reachable through in-application programming. t3-2.2 384 table 3-3: sfcf v alues u nder d ifferent r eset c onditions sc1 1 1. sc1 only applies to sst89e554 and sst89v554. sc0 state of sfcf[1:0] after: power-on or external reset wdt reset or brown-out reset software reset 11 00 (default) x0 10 10 01 x1 11 0 1 10 10 10 0 0 11 11 11 t3-3.2 384
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 13 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 3-4: f lash f lex 51 sfr m emory m ap 8 bytes f8h ipa 1 ffh f0h b 1 ipah f7h e8h iea 1 efh e0h acc 1 e7h d8h dfh d0h psw 1 spcr d7h c8h t2con 1 t2mod rcap2l rcap2h tl2 th2 cfh c0h wdtc 1 c7h b8h ip 1 saden bfh b0h p3 1 sfcf sfcm sfal sfah sfdt sfst iph b7h a8h ie 1 saddr spsr afh a0h p2 1 auxr1 a7h 98h scon 1 sbuf 9fh 90h p1 1 97h 88h tcon 1 tmod tl0 tl1 th0 th1 auxr 8fh 80h p0 1 sp dpl dph wdtd spdr pcon 87h t3-4.3 384 1. sfrs are bit addressable.
14 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 3-5: cpu related sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb acc 1 accumulator e0h acc[7:0] 00h b 1 b register f0h b[7:0] 00h psw 1 program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 82h dpl[7:0] 00h dph data pointer high 83h dph[7:0] 00h ie 1 interrupt enable a8h ea - et2 es0 et1 ex1 et0 ex0 40h iea 1 interrupt enable a e8h - - - - ebo - - - xxxx0xxxb ip 1 interrupt priority reg b8h - - pt2 ps pt1 px1 pt0 px0 xx000000b iph interrupt priority reg high b7h - - pt2h psh pt1h px1h pt0h px0h xx000000b ipa 1 interrupt priority reg a f8h - - - - pbo - - - xxxx0xxxb ipah interrupt priority reg a high f7h - - - - pbo h - - - xxxx0xxxb pcon power control 87h smod1 smod0 bof pof gf1 gf0 pd idl 00010000b auxr auxiliary reg 8eh - - - - - - extram ao xxxxxxx00b auxr1 auxiliary reg 1 a2h - - - - gf2 0 - dps xxxx00x0b t3-5.10 384 1. bit addressable sfrs table 3-6: f lash m emory p rogramming sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sfst superflash status b6h secd1 secd2 secd3 - - flash_busy - - xxxxx0xxb sfcf superflash configuration b1h - iapen - - - - swr bsel x0xxxxxxb sfcm superflash command b2h fie fcm 00h sfdt superflash data b5h superflash data register 00h sfal superflash address low b3h superflash low order byte address register - a 7 toa 0 (sfal) 00h sfah superflash address high b4h superflash high order byte address register - a 15 toa 8 (sfah) 00h t3-6.6 384
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 15 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 3-7: w atchdog t imer sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb wdtc 1 watchdog timer control c0h - - - wdout wdre wdts wdt swdt xxx00x00b wdtd watchdog timer data/reload 85h watchdog timer data/reload 00h t3-7.3 384 1. bit addressable sfrs table 3-8: t imer /c ounters sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb tmod timer/counter mode control 89h timer 1 timer 0 00h gate c/t# m1 m0 gate c/t# m1 m0 tcon 1 1. bit addressable sfrs timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 msb 8ch th0[7:0] 00h tl0 timer 0 lsb 8ah tl0[7:0] 00h th1 timer 1 msb 8dh th1[7:0] 00h tl1 timer 1 lsb 8bh tl1[7:0] 00h t2con 1 timer / counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h t2mod# timer2 mode control c9h---- - -t2oedcenxxxxxx00b th2 timer 2 msb cdh th2[7:0] 00h tl2 timer 2 lsb cch tl2[7:0] 00h rcap2h timer 2 capture msb cbh rcap2h[7:0] 00h rcap2l timer 2 capture lsb cah rcap2l[7:0] 00h t3-8.3 384
16 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 3-9: i nterface sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sbuf serial data buffer 99h sbuf[7:0] indeterminate scon 1 serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h saddr slave address a9h saddr#[7:0] 00h saden slave address mask b9h saden#[7:0] 00h spcr spi control register d5h spie spe dord mstr cpol cpha spr1 spr0 04h spsr spi status register aah spif wcol 00h spdr spi data register 86h spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 00h p0 1 port 0 80h p0[7:0] ffh p1 1 port 1 90h - - - - - - t2ex t2 ffh p2 1 port 2 a0h p2[7:0] ffh p3 1 port 3 b0h rd# wr# t1 t0 int1# int0# txd rxd ffh t3-9.4 384 1. bit addressable sfrs
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 17 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 symbol function secd1 security bit 1. secd2 security bit 2. secd3 security bit 3. please refer to table 4-6 for security lock options. flash_busyflash operation completion polling bit. 1: device is busy with flash operation. 0: device has fully completed the last command. symbol function iapen enable iap operation 0: iap commands are disabled 1: iap commands are enabled swr software reset see ?9.2 software reset? on page 43 bsel program memory block switching bit see figures 3-1 and 3-2. symbol function fie flash interrupt enable. 0: int1# is not reassigned. 1: int1# is re-assigned to signal iap operation completion. external int1# interrupts are ignored. fcm[6:0] flash operation command 000_1011b sector-erase 000_1101b block-erase 000_1100b byte-verify 1 000_1110b byte-program 000_1111b prog-sb1 000_0011b prog-sb2 000_0101b prog-sb3 000_1001b prog-sc0 all other combinations are not implemented, and reserved for future use. 1. byte-verify has a single machine cycle latency and wil l not generate any int1# interrupt regardless of fie. superflash status register (sfst) (read only register) location76543 2 10reset value 0b6h secd1 secd2 secd3 - - flash_busy - - xxxxx0xxb superflash configuration register (sfcf) location76543210reset value 0b1h - iapen ---- swr bsel x0xxxxxxb superflash command register (sfcm) location76543210reset value 0b2h fie fcm6 fcm5 fcm4 fcm3 fcm2 fcm1 fcm0 00000000b
18 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 symbol function sfdt mailbox register for interfacing with flash memory block. (data register). symbol function sfal mailbox register for interfacing with flash memory block. (low order address register). symbol function sfah mailbox register for interfacing with flash memory block. (high order address register). symbol function ea global interrupt enable. 0 = disable 1 = enable et2 timer 2 interrupt enable. es serial interrupt enable. et1 timer 1 interrupt enable. ex1 external 1 interrupt enable. et0 timer 0 interrupt enable. ex0 external 0 interrupt enable. symbol function ebo brown-out interrupt enable. 1 = enable the interrupt 0 = disable the interrupt superflash data register (sfdt) location76543210reset value 0b5h superflash data register 00000000b superflash address registers (sfal) location76543210reset value 0b3h superflash low order byte address register 00000000b superflash address registers (sfah) location76543210reset value 0b4h superflash high order byte address register 00000000b interrupt enable (ie) location76543210reset value a8h ea - et2 es et1 ex1 et0 ex0 00h interrupt enable a (iea) location76543210reset value e8h----ebo---xxxx0xxxb
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 19 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 symbol function pt2 timer 2 interrupt priority bit. ps serial port interrupt priority bit. pt1 timer 1 interrupt priority bit. px1 external interrupt 1 priority bit. pt0 timer 0 interrupt priority bit. px0 external interrupt 0 priority bit. symbol function pt2h timer 2 interrupt priority bit high. psh serial port interrupt priority bit high. pt1h timer 1 interrupt priority bit high. px1h external interrupt 1 priority bit high. pt0h timer 0 interrupt priority bit high. px0h external interrupt 0 priority bit high. symbol function pbo brown-out interrupt priority bit. symbol function pboh brown-out interrupt priority bit high. interrupt priority (ip) location76543210reset value b8h - - pt2 ps pt1 px1 pt0 px0 xx000000b interrupt priority high (iph) location76543210reset value b7h - - pt2h psh pt1h px1h pt0h px0h xx000000b interrupt priority a (ipa) location76543210reset value f8h----pbo---xxxx0xxxb interrupt priority a high (ipah) location76543210reset value f7h----pboh---xxxx0xxxb
20 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 symbol function extram 0: internal expanded ram access. for details, refer to ?data memory? on page 12. 1: external data memory access. ao 0: normal ale 1: ale is normally off. ale is active only during a movx or movc instruction. this will reduce emi. symbol function gf2 general purpose user-defined flag. dps dptr registers select bit. 0: dptr0 is selected. 1: dptr1 is selected. symbol function wdout watchdog output enable. 0: watchdog reset will not be exported on reset pin. 1: watchdog reset if enabled by wdre, will assert reset pin for 32 clocks. wdre watchdog timer reset enable. 0: disable watchdog timer reset. 1: enable watchdog timer reset. wdts watchdog timer reset flag. 0: external hardware reset clears the flag. flag can also be cleared by writing a 1. flag survives if chip reset happened because of watchdog timer overflow. 1: hardware sets the flag on watchdog overflow. wdt watchdog timer refresh. 0: hardware resets the bit when refresh is done. 1: software sets the bit to force a watchdog timer refresh. swdt start watchdog timer. 0: stop wdt. 1: start wdt. auxiliary register (auxr) location76543210reset value 8eh------extramaoxxxxxx00b auxiliary register 1 (auxr1) location76543210reset value a2h----gf20-dpsxxxx00x0b watchdog timer control register (wdtc) location76543210reset value 0c0h--- wdout wdre wdts wdt swdt xxx00x00b
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 21 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 symbol function wdtd initial/reload value in watchdog timer. new value won?t be effective until wdt is set. symbol function spie if both spie and es are set to one, spi interrupts are enabled. spe spi enable bit. 0: disables spi. 1: enables spi and connects ss#, mosi, miso, and sck to pins p1[4], p1[5], p1[6], p1[7]. dord data transmission order. 0: msb first in data transmission. 1: lsb first in data transmission. mstr master/slave select. 0: selects slave mode. 1: selects master mode. cpol clock polarity 0: sck is low when idle (active high). 1: sck is high when idle (active low). cpha clock phase control bit. 0: shift triggered on the leading edge of the clock. 1: shift triggered on the trailing edge of the clock. spr1, spr0 spi clock rate select bits. these two bits control the sck rate of the device configured as master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator frequency, f osc , is as follows: watchdog timer data/reload register (wdtd) location76543210reset value 085h watchdog timer data/reload 00000000b spi control register (spcr) location76543210reset value d5h spie spe dord mstr cpol cpha spr1 spr0 00000100b spr1 spr0 sck = f osc divided by 0 0 1 1 0 1 0 1 4 16 64 128
22 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 symbol function spif upon completion of data transfer, this bit is set to 1. if spie =1 and es =1, an interrupt is then generated. to clear, read spsr and then access spdr. wcol set if the spi data register is written to during data transfer. to clear, read spsr and then access spdr. symbol function smod1 double baud rate bit. if smod1 = 1, timer 1 is used to generate the baud rate. smod0 fe/sm0 selection bit. 0: scon[7] = sm0 1: scon[7] = fe, bof brown-out detection status bit, this bit will not be affected by any other reset. bof should be cleared by software. power-on reset will also clear the bof bit. 0: no brown-out. 1: brown-out occurred pof power-on reset status bit, this bit will not be affected by any other reset. pof should be cleared by software. 0: no power-on reset. 1: power-on reset occurred gf1 general-purpose flag bit. gf0 general-purpose flag bit. pd power-down bit. 0: power-down mode is not activated. 1: activates power-down mode. idl idle mode bit. 0: idle mode is not activated. 1: activates idle mode. spi status register (spsr) location76543210reset value aah spif wcol - - ----00xxxxxxb spi data register (spdr) location76543210reset value 86h spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 00h power control register (pcon) location76543210reset value 87h smod1 smod0 bof pof gf1 gf0 pd idl 00010000b
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 23 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 symbol function fe set smod0 = 1 to access fe bit. 0: no framing error 1: framing error. set by receiver when an invalid stop bit is detected. this bit needs to be cleared by software. sm0 smod0 = 0 to access sm0 bit. serial port mode bit 0 sm1 serial port mode bit 1 sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then ri will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then ri will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. 0: to disable reception. 1: to enable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 - 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission, must be cleared by software. ri receive interrupt flag. set by hardware at the end of the8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. serial port control register (scon) location76543210reset value 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00000000b sm0 sm1 mode description baud rate 1 1. f osc = oscillator frequency 000shift registerf osc /6 (6 clock mode) or f osc / 12 (12 clock mode) 0 1 1 8-bit uart variable 1029-bit uartf osc /32 or f osc /16 (6 clock mode) or f osc /64 or f osc /32 (12 clock mode) 1 1 3 9-bit uart variable
24 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 4.0 flash memory programming the device internal flash memory can be programmed or erased using the following two methods: external host mode in-application programming (iap) mode 4.1 external host programming mode external host programming mode allows the user to pro- gram the flash memory directly without using the cpu. external host mode is entered by forcing psen# from a logic high to a logic low while rst input is being held con- tinuously high. the device will stay in external host mode as long as rst = 1 and psen# = 0. a read-id operation is necessary to ?arm? the device in external host mode, and no other external host mode com- mands can be enabled until a read-id is performed. in external host mode, the internal flash memory blocks are accessed through the re-assigned i/o port pins (see figure 4-1 for details) by an external host, such as a mcu program- mer, a pcb tester or a pc-controlled development board. note: symbol ? signifies a negative pulse and the command is asserted during the low state of prog#/ale input. all other combinations of the above input pins are invalid and may result in unexpected behaviors. note: v il = input low voltage; v ih = input high voltage; v ih1 = input high voltage (xtal, rst); x = don?t care; al = address low order byte; ah = address high order byte; di = data input; do = data output table 4-1: e xternal h ost m ode c ommands for sst89e564/sst89v564 operation rst psen# prog#/ ale ea# p3[7] p3[6] p2[7] p2[6] p0[7:0] p3[5:4] p2[5:0] p1[7:0] read-id v ih1 v il v ih v ih v il v il v il v il do ah al chip-erase v ih1 v il ? v ih v ih v il v il v il xx x block-erase v ih1 v il ? v ih v ih v ih v il v ih xx x sector-erase v ih1 v il ? v ih v ih v il v ih v ih xahal byte-program v ih1 v il ? v ih v ih v ih v ih v il di ah al byte-verify (read) v ih1 v il v ih v ih v ih v ih v il v il do ah al select-block0 v ih1 v il ? v ih v ih v il v il v ih x55h x select-block1 v ih1 v il ? v ih v ih v il v il v ih xa5h x prog-sc0 v ih1 v il ? v ih v ih v il v il v ih x5ah x prog-sb1 v ih1 v il ? v ih v ih v ih v ih v ih xx x prog-sb2 v ih1 v il ? v ih v il v il v ih v ih xx x prog-sb3 v ih1 v il ? v ih v il v ih v il v ih xx x t4-1.4 384
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 25 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 note: symbol ? signifies a negative pulse and the command is asserted during the low state of prog#/ale input. all other combinations of the above input pins are invalid and may result in unexpected behaviors. note: v il = input low voltage; v ih = input high voltage; v ih1 = input high voltage (xtal, rst); x = don?t care; al = address low order byte; ah = address high order byte; di = data input; do = data output; a[15:13] = 0xxb for block 0 and a[15:13] = 111b for block 1 figure 4-1: i/o p in a ssignments for e xternal h ost m ode table 4-2: e xternal h ost m ode c ommands for sst89e554/sst89v554 operation rst psen# prog#/ ale ea# p3[7] p3[6] p2[7] p2[6] p0[7:0] p3[5:4] p2[5:0] p1[7:0] read-id v ih1 v il v ih v ih v il v il v il v il do ah al chip-erase v ih1 v il ? v ih v ih v il v il v il xx x block-erase v ih1 v il ? v ih v ih v ih v il v ih x a[15:13] x sector-erase v ih1 v il ? v ih v ih v il v ih v ih xahal byte-program v ih1 v il ? v ih v ih v ih v ih v il di ah al byte-verify (read) v ih1 v il v ih v ih v ih v ih v il v il do ah al prog-sc0 v ih1 v il ? v ih v ih v il v il v ih x5ah x prog-sc1 v ih1 v il ? v ih v ih v il v il v ih x aah x prog-sb1 v ih1 v il ? v ih v ih v ih v ih v ih xx x prog-sb2 v ih1 v il ? v ih v il v il v ih v ih xx x prog-sb3 v ih1 v il ? v ih v il v ih v il v ih xx x t4-2.0 384 flash control signals address bus a7-a0 flash control signals address bus a13-a8 input/ output data bus port 0 v ss xtal1 xtal2 ready/busy# port 3 v dd rst port 2 port 1 ea# ale / prog# psen# 7 6 5 a15 a14 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 0 7 6 0 address bus a15-a14 384 ill f01.1
26 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 4.1.1 product identification the read-id command accesses the signature bytes that identify the device and the manufacturer as sst. external programmers primarily use these signature bytes in the selection of programming algorithms. the read-id com- mand is selected by the command code of 0h on p3[7:6] and p2[7:6]. see figure 4-2 for timing waveforms. 4.1.2 arming command an arming command sequence must take place before any external host mode sequence command is recog- nized by the device. this prevents accidental triggering of external host mode commands due to noise or program- mer error. the arming command is as follows: 1. psen# goes low while rst is high. this will get the machine in external host mode, re-configuring the pins, and turning on the on-chip oscillator. 2. a read-id command is issued, and after 1 ms the external host mode commands can be issued. after the above sequence, all other external host mode commands are enabled. before the read-id command is received, all other external host mode commands received are ignored. 4.1.3 detail explanation of the external host mode commands the external host mode commands are read-id, chip- erase, block-erase, sector-erase, byte-program, byte- verify, prog-sb1, prog-sb2, prog-sb3, prog-sc0, prog- sc1, select-block0, select-block1. see tables 4-1 and 4-2 for all signal logic assignments, figure 4-1 for i/o pin assignments, and table 4-7 for the timing parameters. the critical timing for all erase and program commands is gen- erated by an on-chip flash memory controller. the high-to- low transition of the prog# signal initiates the erase or program commands, which are synchronized internally. the read commands are asynchronous reads, indepen- dent of the prog# signal level. following is a detailed description of the external host mode commands: the select-block0 command enables block 0 to be pro- grammed in external host mode. once this command is executed, all subsequent external host commands will be directed at block 0. see figure 4-3 for timing waveforms. this command applies to sst89e564/sst89v564 only. the select-block1 command enables block 1 (8 kbyte block) to be programmed. once this command is exe- cuted, all subsequent external host commands that are directed to the address range below 2000h will be directed at block 1. the select-block1 command only affects the lowest 8 kbyte of the program address space. for addresses greater than or equal to 2000h, block 0 is accessed by default. upon entering external host mode, block 1 is selected by default. see figure 4-3 for timing waveforms. this command applies to sst89e564/ sst89v564 only. the chip-erase, block-erase, and sector-erase com- mands are used for erasing all or part of the memory array. erased data bytes in the memory array will be erased to ffh. memory locations that are to be pro- grammed must be in the erased state prior to program- ming. the chip-erase command erases all bytes in both memory blocks, regardless of any previous select-block0 or select- block1 commands. chip-erase ignores the security lock status and will erase the security lock, returning the device to its unlocked state. the chip-erase command will also erase the sc0 bit. upon completion of chip-erase com- mand, block 1 will be the selected block. see figure 4-4 for timing waveforms. the block-erase command erases all bytes in the selected memory blocks. this command will not be executed if the security lock is enabled. the selection of the memory block to be erased is determined by the prior execution select- block0 or select-block1 command. see figure 4-6 for the timing waveforms. the sector-erase command erases all of the bytes in a sector. the sector size for the flash memory is 128 bytes. this command will not be executed if the security lock is enabled. see figure 4-7 for timing waveforms. the byte-program command is used for programming new data into the memory array. programming will not take place if any security locks are enabled. see figure 4-8 for timing waveforms. table 4-3: s ignature b ytes address data manufacturer?s id 30h bfh device id sst89e564 31h 93h sst89v564 31h 92h sst89e554 31h 9bh sst89v554 31h 9ah t4-3.4 384
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 27 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 the byte-verify command allows the user to verify that the device correctly performed an erase or program com- mand. this command will be disabled if any security locks are enabled. see figure 4-11 for timing waveforms. the prog-sb1, prog-sb2, prog-sb3 commands program the security bits, the functions of these bits are described in the security lock section and also in table 8-1. once pro- grammed, these bits can only be erased through a chip- erase command. see figure 4-9 for timing waveforms. prog-sc0 command programs sc0 bit, which determines the state of sfcf[0] out of reset. once programmed, sc0 can only be restored to an erased state via a chip-erase command. see figure 4-10 for timing waveforms. prog-sc1 command programs sc1 bit, which determines the state of sfcf[1] out of reset. once programmed, sc1 can only be restored to an erased state via a chip-erase command. see figure 4-10 for timing waveforms. prog- sc1 is for sst89e554/sst89v554 only. 4.1.4 external host mode clock source in external host mode, an internal oscillator will provide clocking for the device. the on-chip oscillator will be turned on as the device enters external host mode; i.e. when psen# goes low while rst is high. during external host mode, the cpu core is held in reset. upon exit from exter- nal host mode, the internal oscillator is turned off. 4.1.5 flash operation status detection via external host handshake the device provides two methods for an external host to detect the completion of a flash memory operation to opti- mize the program or erase time. the end of a flash mem- ory operation cycle can be detected by: 1. monitoring the ready/busy# bit at p3[3]; 2. monitoring the data# polling bit at p0[3]. 4.1.5.1 ready/busy# (p3[3]) the progress of the flash memory programming can be monitored by the ready/busy# output signal. p3[3] is driven low, some time after ale/prog# goes low during a flash memory operation to indicate the busy# status of the flash control unit (fcu). p3[3] is driven high when the flash programming operation is completed to indicate the ready status. 4.1.5.2 data# polling (p0[3]) during a program operation, any attempts to read (byte- verify), while the device is busy, will receive the comple- ment of the data of the last byte loaded (logic low, i.e. ?0? for an erase) on p0[3] with the rest of the bits ?0?. during a pro- gram operation, the byte-verify command is reading the data of the last byte loaded, not the data at the address specified. 4.1.6 step-by-step instructions to perform external host mode commands to program data into the memory array, apply power supply voltage (v dd ) to v dd and rst pins, and per- form the following steps: 1. maintain rst high and set psen# from logic high to low, in sequence according to the appropriate timing diagram. 2. raise ea# high (v ih ). 3. issue read-id command to enable the external host mode. 4. verify that the memory blocks or sectors for pro- gramming is in the erased state, ffh. if they are not erased, then erase them using the appropriate erase command. 5. select the memory location using the address lines (p3[5:4], p2[5:0], p1[7:0]). 6. present the data in on p0[7:0]. 7. pulse ale/prog#, observing minimum pulse width. 8. wait for low to high transition on ready/busy# (p3[3]). 9. repeat steps 5 - 8 until programming is finished. 10. verify the flash memory contents.
28 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 4.1.7 flash memory programming timing diagrams with external host mode figure 4-2: r ead -id reads chip signature and identification registers at the addressed location. figure 4-3: s elect -b lock 1 / s elect -b lock 0 enables the selection of either of the flash memory blocks prior to issuing a byte-verify, block-erase, sector- erase, or byte-program. these commands apply to sst89e564/sst89v564 only. 384 ill f02.3 0030h t su t es rst psen# ale/prog# ea# p3[5:4] ,p2[5:0] ,p1 p2[7:6] ,p3[7:6] p0 0000b t rd bfh 0031h 0000b t rd device id device id = 93h for sst89e564 92h for sst89v564 9bh for sst89e554 9ah for sst89v554 rst psen# ale/prog# ea# p3[3] p3[5:4], p2[5:0] a5h/55h t psb t prog t ads 384 ill f56.1 p3[7:6], p2[7:6] 1001b t dh t su t es
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 29 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 4-4: c hip -e rase erases both flash memory blocks. security lock is ignored and the security bits are erased too. figure 4-5: b lock -e rase for sst89e564/sst89v564 erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] 0001b t ce t prog t ads 384 ill f03.1 t es t su t dh ea# rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] 1101b t be t prog t su t ads 384 ill f04.2 t es t dh ea#
30 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 4-6: b lock -e rase for sst89e554/sst89v554 erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. figure 4-7: s ector -e rase erases the addressed sector if the security lock is not activated on that flash memory block. rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] p3[5:4], p2[5:0] 1101b ah t be t prog t su t ads 384 ill f21.1 t es t dh ea# rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] p3[5:4], p2[5:0] 1011b ah t se t prog t ads 384 ill f05.1 p1 al t dh t su t es ea#
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 31 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 4-8: b yte -p rogram programs the addressed code byte if the byte location has been successfully erased and not yet programmed. byte-program operation is only allowed when the security lock is not activated on that flash memory block. figure 4-9: p rog -sb1 / p rog -sb2 / p rog -sb3 programs the security bits sb1, sb2 and sb3 respectively. only a chip-erase will erase a programmed security bit. rst psen# ale/prog# ea# p3[3] p3[5:4], p2[5:0] p1 ah al t ps t prog t ads 384 ill f06.2 p0 p3[7:6], p2[7:6] di 1110b t dh t su t es rst psen# ale/prog# ea# p3[3] t ps t prog t ads 384 ill f49.2 p3[7:6], p2[7:6] 1111b / 0011b / 0101b t dh t su t es
32 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 4-10: p rog -sc0 / p rog -sc1 programs the start-up configuration bit sc0/sc1. only a chip-erase will erase a programmed sc0/sc1 bit. prog-sc1 applies to sst89e554/sst89v554 only. figure 4-11: b yte -v erify reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. rst psen# ale/prog# ea# p3[3] p3[5:4], p2[5:0] 5ah / aah t ps t prog t ads 384 ill f52.5 p3[7:6], p2[7:6] 1001b t dh t su t es 384 ill f08.1 p3[5:4], p2[5:0] al do 1100b p3[7:6], p2[7:6] t su rst psen# ale/prog# ea# p0 p1 t ala t oa t aha ah t es
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 33 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 4.2 in-application programming mode the device offers either 72 or 40 kbyte of in-application programmable flash memory. during in-application pro- gramming, the cpu of the microcontroller enters iap mode. the two blocks of flash memory allow the cpu to execute user code from one block, while the other is being erased or reprogrammed concurrently. the cpu may also fetch code from an external memory while all internal flash is being reprogrammed. the mailbox registers (sfst, sfcm, sfal, sfah, sfdt and sfcf) located in the spe- cial function register (sfr), control and monitor the device?s erase and program process. table 4-6 outlines the commands and their associated mailbox register settings. 4.2.1 in-application programming mode clock source during iap mode, both the cpu core and the flash control- ler unit are driven off the external clock. however, an inter- nal oscillator will provide timing references for program and erase operations. the internal oscillator is only turned on when required, and is turned off as soon as the flash oper- ation is completed. 4.2.2 memory bank selection for in-application programming mode with the addressing range limited to 16 bit, only 64 kbyte of program address space is ?visible? at any one time. as shown in table 4-4, bank selection (the configuration of ea# and sfcf[1:0]), allows block 1 memory to be overlaid on the lowest 8 kbyte of block 0 memory, making block 1 reachable. the same concept is employed to allow both block 0 and block 1 flash to be accessible to iap opera- tions. code from a block that is not visible may not be used as a source to program another address. however, a block that is not ?visible? may be programmed by code from the other block through mailbox registers. the device allows iap code in one block of memory to pro- gram the other block of memory, but may not program any location in the same block. if an iap operation originates physically from block 0, the target of this operation is implic- itly defined to be in block 1. if the iap operation originates physically from block 1, then the target address is implicitly defined to be in block 0. if the iap operation originates from external program space, then, the target will depend on the address and the state of bank select. 4.2.3 iap enable bit the iap enable bit, sfcf[6], enables in-application pro- gramming mode. until this bit is set all flash programming iap commands will be ignored. 4.2.4 in-application programming mode commands all of the following commands can only be initiated in the iap mode. in all situations, writing the control byte to the sfcm register will initiate all of the operations. all com- mands will not be enabled if the security locks are enabled on the selected memory block. the program command is for programming new data into the memory array. the portion of the memory array to be programmed should be in the erased state, ffh. if the memory is not erased, it should first be erased with an appropriate erase command. warning: do not attempt to write (program or erase) to a block that the code is cur- rently fetching from. this will cause unpredictable pro- gram behavior and may corrupt program data. the block-erase command erases all bytes in one of the two memory blocks. the selection of the memory block to be erased is determined by the source of block-erase command, as defined in table 4-4. table 4-4: iap a ddress r esolution for sst89e564/sst89v564 ea# sfcf[1:0] address of iap inst. tar get address block being programmed 1 00 >= 2000h (block 0) >= 2000h (block 0) none 1 1. no operation is performed because code from one bloc k may not program the same originating block 1 00 >= 2000h (block 0) < 2000h (block 1) block 1 1 00 < 2000h (block 1) any (block 0) block 0 1 01, 10, 11 any (block 0) >= 2000h (block 0) none 1 1 01, 10, 11 any (block 0) < 2000h (block 1) block 1 0 00 from external >= 2000h (block 0) block 0 0 00 from external < 2000h (block 1) block 1 0 01, 10, 11 from external any (block 0) block 0 t4-4.5 384
34 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 the sector-erase command erases all of the bytes in a sector. the sector size for the flash memory blocks is 128 bytes. the selection of the sector to be erased is deter- mined by the contents of sfah and sfal. the byte-program command programs data into a single byte. the address is determined by the contents of sfah and sfal. the data byte is in sfdt. the byte-verify command allows the user to verify that the device has correctly performed an erase or program com- mand. byte-verify command returns the data byte in sfdt if the command is successful. the user is required to check that the previous flash operation has fully completed before issuing a byte-verify. byte-verify command execution time is short enough that there is no need to poll for command completion and no interrupt is generated. prog-sb3, prog-sb2, prog-sb1 commands are used to program the security bits (see table 8-1). completion of any of these commands, the security options will be updated immediately. security bits previously in un-programmed state can be programmed by these commands. prog-sb3, prog-sb2 and prog-sb1 commands should only reside in block 1. prog-sc0 command is used to program the sc0 bit. this command only changes the sc0 bit and has no effect on bsel bit until after a reset cycle. sc0 bit previously in un-programmed state can be pro- grammed by this command. the prog-sc0 command should reside only in block 1. prog-sc1 command is used to program the sc1 bit. this command only changes the sc1 bit and has no effect on bsel bit until after a reset cycle. sc1 bit previously in un-programmed state can be pro- grammed by this command. the prog-sc1 command should reside only in block 1. there are no iap counterparts for the external host com- mands select-block0 and select-block1. 4.2.5 polling a command that uses the polling method to detect flash operation completion should poll on the flash_busy bit (sfst[2]). when flash_busy de-asserts (logic 0), the device is ready for the next operation. movc instruction may also be used for verification of the programming and erase operation of the flash memory. movc instruction will fail if it is directed at a flash block that is still busy. 4.2.6 interrupt termination if interrupt termination is selected, (sfcm[7] is set), then an interrupt (int1) will be generated to indicate flash opera- tion completion. under this condition, the int1 becomes an internal interrupt source. the int1# pin can now be used as a general purpose port pin and it cannot be the source of external interrupt 1 during in-application programming. in order to use an interrupt to signal flash operation termi- nation. ex1 and ea bits of ie register must be set. the it1 bit of tcon register must also be set for edge trigger detection. .
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 35 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 . table 4-5: i n -a pplication p rogramming m ode c ommands 1 for sst89e564/sst89v564 operation sfcm [6:0] 2 sfdt [7:0] sfah [7:0] sfal [7:0] block-erase 3 0dh 55h x 4 x sector-erase 3 0bh x ah 5 al 6 byte-program 3 0eh di 7 ah al byte-verify (read) 3 0ch do 8 ah al prog-sb1 9 0fh aah x x prog-sb2 9 03h aah x x prog-sb3 9 05h aah x x prog-sc0 9 09h aah 5ah x t4-5.8 384 1. sfcf[6]=1 enables iap commands; sfcf[6]=0 disables iap commands. 2. interrupt/polling enable for flash operation completion sfcm[7] =1: interrupt enable for flash operation completion 0: polling enable for flash operation completion 3. refer to table 4-4 for address resolution 4. x can be v il or v ih , but no other value. 5. ah = address high order byte 6. al = address low order byte 7. di = data input 8. do = data output all other values are in hex 9. instruction must be located in block 1 table 4-6: i n -a pplication p rogramming m ode c ommands 1 for sst89e554/sst89v554 1. sfcf[6]=1 enables iap commands; sfcf[6]=0 disables iap commands. operation sfcm [6:0] 2 2. interrupt/polling enable for flash operation completion sfcm[7] =1: interrupt enable for flash operation completion 0: polling enable for flash operation completion sfdt [7:0] sfah [7:0] sfal [7:0] block-erase 3 3. refer to table 4-4 for address resolution 0dh 55h ah 4 4. sfah[7]=0: selects block 0; sfah[7:5] = 111b selects block 1 x 5 5. x can be v il or v ih , but no other value. sector-erase 3 0bh x ah 6 6. ah = address high order byte al 7 7. al = address low order byte byte-program 3 0eh di 8 8. di = data input ah al byte-verify (read) 3 0ch do 9 9. do = data output all other values are in hex ah al prog-sb1 10 10. instruction must be located in block 1 0fh aah x x prog-sb2 10 03h aah x x prog-sb3 10 05h aah x x prog-sc0 10 09h aah 5ah x prog-sc1 10 09h aah aah x t4-6.0 384
36 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 5.0 timers/counters the device has three 16-bit registers that can be used as either timers or event counters. the three timers/counters are denoted timer 0 (t0), timer 1 (t1), and timer 2 (t2). each is designated a pair of 8-bit registers in the sfrs. the pair consists of a most significant (high) byte and least significant (low) byte. the respective registers are tl0, th0, tl1, th1, tl2, and th2. 6.0 serial i/o 6.1 enhanced univer sal aysnchronous receiver/transmitter (uart) the device serial i/o port is a full duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respec- tively, while the software is performing other tasks. the transmit and receive registers are both located in the serial data buffer (sbuf) special function register. writ- ing to the sbuf register loads the transmit register, and reading from the sbuf register obtains the contents of the receive register. the uart has four modes of operation which are selected by the serial port mode specifier (sm0 and sm1) bits of the serial port control (scon) special function register. in all four modes, transmission is initiated by any instruction that uses the sbuf register as a destination register. reception is initiated in mode 0 when the receive interrupt (ri) flag bit of the serial port control (scon) sfr is cleared and the reception enable/ disable (ren) bit of the scon register is set. reception is initiated in the other modes by the incoming start bit if the ren bit of the scon register is set. 6.1.1 framing error detection framing error detection allows the serial port to auto- matically check for valid stop bits in modes 1, 2 or 3. if a stop bit is missing the framing error bit (fe) will be set. the software can then check this bit after a recep- tion to detect communication errors. the fe bit must be cleared by software. the fe bit is located in scon and shares the same bit address as sm0. the smod0 bit located in the pcon reg- ister determines which of these two bits is accessed. when smod0 = 0, scon[7] will act as sm0. when smod0 = 1, scon[7] will act as fe. 6.1.2 automatic address recognition automatic address recognition (aar) reduces the cpu time required to service the serial port in a multiprocessor environment. when using aar, the serial port hardware will only generate an interrupt when it receives its own address, thus eliminating the software overhead required to compare addresses. table 4-7: f lash m emory p rogramming /v erification p arameters parameter 1,2 symbol min max units reset setup time t su 3s read-id command width t rd 1 s psen# setup time t es 1.125 s address, command, data setup time t ads 0ns chip-erase time t ce 125 ms block-erase time t be 100 ms sector-erase time t se 30 ms program setup time t prog 1.2 s address, command, data hold t dh 0ns byte-program time 3 t pb 50 s select-block program time t psb 500 ns security bit program time t ps 80 s verify command delay time t oa 50 ns verify high order address delay time t aha 50 ns verify low order address delay time t ala 50 ns t4-7.5 384 1. program and erase times will scale inversel y proportional to programming clock frequency. 2. all timing measurements are from the 50% of the input to 50% of the output. 3. each byte must be erased before programming.
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 37 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 aar is only available when using the serial port in either mode 2 or 3. setting the sm2 bit in scon enables aar. each slave must have its sm2 bit set when waiting for an address (9th bit = 1). the receive interrupt (ri) flag will only be set when the received byte matches either the given or broadcast address. the slave then clears its sm2 bit to enable reception of data bytes (9th bit = 0) from the master. the master can selectively communicate with groups of slaves by sending the given address. addressing all slaves is also possible by sending the broadcast address. the saddr and saden special function registers define these addresses for each slave. saddr specifies a slaves individual address and saden is a mask byte that defines don?t-care bits to form the given address when combined with saddr. the following is an example: in this example slave 1 can be distinguished from slave 2 by using bits 0 and 1. slave 1 will not respond to an address that has bit 1 set to 1 while slave 2 will. similarly, slave 2 will not respond to an address that has bit 0 set to 0 while slave 1 will. both slaves will respond to an address of 1111 0x01b so this is the broadcast address. the broad- cast addresses is formed by the logical or of saddr and saden with 0s treated as don?t-care bits. 6.2 serial peripheral interface (spi) the device spi allows for high-speed full-duplex synchro- nous data transfer between the device and other compati- ble spi devices. figure 6-1 shows the correspondence between master and slave spi devices. the sck pin is the clock output and input for the master and slave modes, respectively. the spi clock generator will start following a write to the master devices spi data register. the written data is then shifted out of the mosi pin on the master device into the mosi pin of the slave device. following a complete transmission of one byte of data, the spi clock generator is stopped and the spif flag is set. an spi interrupt request will be gener- ated if the spi interrupt enable bit (spie) and the serial port interrupt enable bit (es) are both set. an external master drives the slave select input pin, ss#/ p1[4], low to select the spi module as a slave. if ss#/p1[4] has not been driven low, then the slave spi unit is not active and the mosi/p1[5] port can also be used as an input port pin. cpha and cpol control the phase and polarity of the spi clock. figures 6-2 and 6-3 show the four possible combina- tions of these two bits. figure 6-1: spi m aster - slave i nterconnection uart slave 1 saddr = 1111 0001 saden = 1111 1010 given = 1111 0x0x uart slave 2 saddr = 1111 0011 saden = 1111 1001 given = 1111 0xx1 384 ill f53.1 8-bit shift register msb master lsb spi clock generator miso miso mosi mosi sck sck ss# ss# 8-bit shift register msb slave lsb v ih
38 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 6-2: spi t ransfer f ormat with cpha = 0 figure 6-3: spi t ransfer f ormat with cpha = 1 384 ill f54.1 msb sck cycle # (for reference) sck (cpol=0) sck (cpol=1) mosi (from master) miso (from slave) ss# (to slave) 6 12345678 5 msb * not defined, but normally msb of next received byte 654321lsb * 4 3 2 1 lsb 384 ill f55.1 msb sck cycle # (for reference) sck (cpol=0) sck (cpol=1) mosi (from master) miso (from slave) ss# (to slave) 6 12345678 5 msb * not defined but normally lsb of previously transmitted character 654321 lsb * 4 3 2 1 lsb
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 39 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 7.0 watchdog timer the device offers a programmable watchdog timer (wdt) for fail safe protection against software deadlock and auto- matic recovery. to protect the system against software deadlock, the user software must refresh the wdt within a user-defined time period. if the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (wdre= 1). the software can be designed such that the wdt times out if the program does not work properly. the wdt in the device uses the system clock (xtal1) as its time base. so strictly speaking, it is a watchdog counter rather than a watchdog timer. the wdt register will incre- ment every 344064 crystal clocks. the upper 8-bits of the time base register (wdtd) are used as the reload register of the wdt. the wdts flag bit is set by wdt overflow and is not changed by wdt reset. user software can clear wdts by writing ?1? to it. figure 7-1 provides a block diagram of the wdt. two sfrs (wdtc and wdtd) control watchdog timer operation. during idle mode, wdt operation is temporarily sus- pended, and resumes upon an interrupt exit from idle. the time-out period of the wdt is calculated as follows: period = (255 - wdt) * 344064 * 1/f osc where wdt is the value loaded into the wdt register and f osc is the oscillator frequency. figure 7-1: b lock d iagram of p rogrammable w atchdog t imer 384 ill f10.2 wdt upper byte wdt reset internal reset 344064 clks counter clk (xtal1) ext. rst wdtc wdtd
40 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 8.0 security lock the security lock protects against software piracy and prevents the contents of the flash from being read by unau- thorized parties. it also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. there are two different types of security locks in the device security lock system: hard lock and softlock. 8.1 hard lock when hard lock is activated, movc or iap instructions executed from an unlocked or softlocked program address space, are disabled from reading code bytes in hard locked memory blocks (see table 8-2). hard lock can either lock both flash memory blocks or just lock the 8 kbyte flash memory block (block 1). all external host and iap commands except for chip-erase are ignored for memory blocks that are hard locked. 8.2 softlock softlock allows flash contents to be altered under a secure environment. this lock option allows the user to update program code in the softlocked memory block through in- application programming mode under a predetermined secure environment. for example, if block 1 (8k) memory block is locked (hard locked or softlocked), and block 0 (64k for sst89e564/sst89v564) memory block is soft- locked, code residing in block 1 can program block 0. the following iap mode commands issued through the com- mand mailbox register, sfcm, executed from a locked (hard locked or softlocked) block, can be operated on a softlocked block: block-erase, sector-erase, byte-pro- gram and byte-verify. in external host mode, softlock behaves the same as a hard lock. 8.3 security lock status the three bits that indicate the device security lock status are located in sfst[7:5]. as shown in figure 8- 1 and table 8-1, the three security lock bits control the lock status of the primary and secondary blocks of memory. there are four distinct levels of security lock status. in the first level, none of the security lock bits are programmed and both blocks are unlocked. in the second level, although both blocks are now locked and cannot be programmed, they are available for read operation via byte-verify. in the third level, three differ- ent options are available: block 1 hard lock / block 0 softlock, softlock on both blocks, and hard lock on both blocks. locking both blocks is the same as level 2 except read operation isn?t available. the fourth level of security is the most secure level. it doesn?t allow read/program of internal memory or boot from external memory. please note that for unused combinations of the security lock bits, the chip will default to level 4 status. for details on how to program the security lock bits refer to the external host mode and in-application programming section. figure 8-1: s ecurity l ock l evels notes: p = programmed (cell logic state = 0), u = unprogrammed (cell logic state = 1), n = not locked, l = hard locked, s = sof tlocked. level 1 level 2 level 3 level 4 uuu/nn puu/ss upp/ll ppu/ls upu/ss ppp/ll 384 ill f38.2 pup/ll upp/ll uup/ls
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 41 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 8-1: s ecurity l ock o ptions level security lock bits 1,2 security status of: security type sfst[7:5] sb1 sb2 1 sb3 1 block 1 block 0 1 000 u u u unlock unlock no security features are enabled. 2 100 p u u softlock softlock movc instructions executed from external program memory are dis- abled from fetching code bytes from internal memory, ea# is sampled and latched on reset, and further pro- gramming of the flash is disabled. 3 011 101 u p p u p p hard lock hard lock level 2 plus verify disabled, both blocks locked. 010 u p u softlock softlock level 2 plus verify disabled. code in block 1 may program block 0 and vice versa. 110 001 p u p u u p hard lock softlock level 2 plus verify disabled. code in block 1 may program block 0. 4 111 p p p hard lock hard lock same as level 3 hardlock/hardlock, but mcu will start code execution from the internal memory regardless of ea#. t8-1.7 384 1. p = programmed (cell logic state = 0), u = unprogrammed (cell logic state = 1). 2. sfst[7:5] = security lock decoding bits (secd)
42 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 8-2: s ecurity l ock a ccess t able level sfst[7:5] source address target address 1 external host byte-verify allowed 2 iap byte-verify allowed movc allowed on 564 movc allowed on 554 4 111b (hard lock on both blocks) block 0/1 block 0/1 n n y y external n/a n n n external block 0/1 n n n n external n/a n n n 3 011b/101b (hard lock on both blocks) block 0/1 block 0/1 n n y y external n n n y external block 0/1 n n n n external n/a n y y 001b/110b (block 0 = softlock, block 1 = hard lock) block 0 block 0 n n y y block 1 n n n n external n/a n n y block 1 block 0 n y y y block 1 n n y y external n/a n n y external block 0/1 n n n n external n/a n y y 010b (softlock on both blocks) block 0 block 0 n n y y block 1 n y y y external n/a n n y block 1 block 0 n y y y block 1 n n y y external n/a n n y external block 0/1 n n n n external n/a n y y 2 100b (softlock on both blocks) block 0 block 0 y n y y block 1 y y y y external n/a n n y block 1 block 0 y y y y block 1 y n y y external n/a n n y external block 0/1 y n n n external n/a n y y 1 000b (unlock) block 0 block 0 y n y y block 1 y y y y external n/a n n y block 1 block 0 y y y y block 1 y n y y external n/a n n y external block 0/1 y y n y external n/a n y y t8-2.1 384 1. location of movc instruction 2. external host byte-verify access does not depend on a source address.
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 43 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 9.0 reset a system reset initializes the mcu and begins program execution at program memory location 0000h. the reset input for the device is the rst pin. in order to reset the device, a logic level high must be applied to the rst pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ale, psen# are weakly pulled high dur- ing reset. during reset, ale and psen# output a high level in order to perform a proper reset. this level must not be affected by external element. a system reset will not affect the 1 kbyte of on-chip ram while the device is running, however, the contents of the on-chip ram during power up are indeterminate. following reset, all special function registers (sfr) return to their reset values outlined in tables 3-5 to 3-9. 9.1 power-on reset at initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algo- rithm has weakly pulled all pins high. powering up the device without a valid reset could cause the mcu to start executing instructions from an indeterminate location. such undefined states may inadvertently cor- rupt the code in the flash. when power is applied to the device, the rst pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. an example of a method to extend the rst signal is to imple- ment a rc circuit by connecting the rst pin to v dd through a 10 f capacitor and to v ss through an 8.2k ? resistor as shown in figure 9-1. note that if an rc circuit is being used, provisions should be made to ensure the v dd rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milliseconds. for a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. this method maintains the necessary relationship between v dd and rst to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. for more information on system level design techniques, please review design consider- ations for the sst flashflex51 family microcontroller application note. figure 9-1: p ower - on r eset c ircuit 9.2 software reset the software reset is executed by changing sfcf[1] (swr) from ?0? to ?1?. a software reset will reset the pro- gram counter to address 0000h. all sfr registers will be set to their reset values, except sfcf[1] (swr), wdtc[2] (wdts), and ram data will not be altered. 9.3 brown-out detection reset the device includes a brown-out detection circuit to protect the system from severe v dd fluctuations. for brown-out voltage parameters, please refer to tables 10-3 and 10-4. brown-out interrupt can be enabled by setting the ebo bit in iea register (address e8h, bit 3). if ebo bit is set and a brown-out condition occurs, a brown-out interrupt will be generated to execute the program at location 004bh. it is required that the ebo bit be cleared by software after the brown-out interrupt is serviced. clearing ebo bit when the brown-out condition is active will properly reset the device. if brown-out interrupt is not enabled, a brown-out condition will reset the program to resume execution at location 0000h. 9.4 interrupt priority and polling sequence the device supports eight interrupt sources under a four level priority scheme. table 9-1 summarizes the polling sequence of the supported interrupts. note that the spi serial interface and the uart share the same interrupt vector. 384 ill f31.2 v dd v dd 10f + - 8.2k sst89e5x4/v5x4 rst xtal2 xtal1 c 1 c 2
44 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 9.5 power-saving modes the device provides three power saving modes of opera- tion for applications where power consumption is critical. the three power saving modes are: idle, power down and standby (stop clock). 9.5.1 idle mode idle mode is entered setting the idl bit in the pcon regis- ter. in idle mode, the program counter (pc) is stopped. the system clock continues to run and all interrupts and periph- erals remain active. the on-chip ram and the special func- tion registers hold their data during this mode. the device exits idle mode through either a system inter- rupt or a hardware reset. exiting idle mode via system interrupt, the start of the interrupt clears the idl bit and exits idle mode. after exit the interrupt service routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. a hardware reset starts the device similar to a power-on reset. 9.5.2 power down mode the power down mode is entered by setting the pd bit in the pcon register. in the power down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. to retain the on-chip ram and all of the spe- cial function registers? values, the minimum v dd level is 2.0v. the device exits power down mode through either an enabled external level sensitive interrupt or a hardware reset. the start of the interrupt clears the pd bit and exits power down. holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. after exit the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked power down mode. a hard- ware reset starts the device similar to power-on reset. to exit properly out of power down, the reset or external interrupt should not be executed before the v dd line is restored to its normal operating voltage. be sure to hold v dd voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). 9.5.3 standby mode (stop clock) standby mode is similar to power down mode, except that power down mode is initiated by a software command and standby mode is initiated by external hardware gating off the external clock to the device.the on-chip sram and sfr data are maintained in standby mode. the device resumes operation at the next instruction when the clock is reapplied to the part. table 9-2 outlines the different power-saving modes, includ- ing entry and exit procedures and mcu functionality. table 9-1: i nterrupt p olling s equence description interrupt flag vector address interrupt enable interrupt priority arbitration ranking wake-up power down ext. int0 ie0 0003h ex0 px0/h 1(highest) yes brown-out bof 004bh ebo pbo/h 2 no t0 tf0 000bh et0 pt0/h 3 no ext. int1 ie1 0013h ex1 px1/h 4 yes t1 tf1 001bh et1 pt1/h 5 no uart/spi ti/ri/spif 0023h es ps/h 6 no t2 tf2, exf2 002bh et2 pt2/h 7 no t9-1.2 384
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 45 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 9-2: p ower s aving m odes mode initiated by state of mcu exited by idle mode software (set idl bit in pcon) clk is running. interrupts, serial port and tim- ers/counters are active. pro- gram counter is stopped. ale and psen# signals at a high level during idle. all registers remain unchanged. enabled interrupt or hardware reset. start of interrupt clears idl bit and exits idle mode, after the isr reti instruction, program resumes execu- tion beginning at the instruction follow- ing the one that invoked idle mode. a user could consider placing two or three nop instructions after the instruction that invokes idle mode to eliminate any problems. a hardware reset restarts the device similar to a power-on reset. power down mode software (set pd bit in pcon) clk is stopped. on-chip sram and sfr data is main- tained. ale and psen# sig- nals at a low level during power down. external inter- rupts are only active for level sensitive interrupts, if enabled. enabled external level sensitive inter- rupt or hardware reset. start of inter- rupt clears pd bit and exits power down mode, after the isr reti instruction program resumes execution beginning at the instruction following the one that invoked power down mode. a user could consider placing two or three nop instructions after the instruction that invokes power down mode to eliminate any problems. a hardware reset restarts the device sim- ilar to a power-on reset. standby (stop clock) mode external hardware gates off the external clock input to the mcu. this gating should be synchronized with an input clock transition (low-to-high or high-to-low). clk is frozen. on-chip sram and sfr data is maintained. ale and psen# are main- tained at the levels prior to the clock being frozen. gate on external clock. program exe- cution resumes at the instruction fol- lowing the one during which the clock was gated off. t9-2.6 384
46 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 9.6 clock input options shown in figure 9-2 are the input and output of an internal inverting amplifier (xtal1, xtal2), which can be config- ured for use as an on-chip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. at start-up, the external oscillator may encounter a higher capacitive load at xtal1 due to interaction between the amplifier and its feedback capacitance. however, the capacitance will not exceed 15 pf once the external signal meets the v il and v ih specifications. 9.7 recommended capa citor values for crystal oscillator crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one applica- tion to another. c1 and c2 should be adjusted appropri- ately for each design. the table below, shows the typical values for c1 and c2 at a given frequency. if following the satisfactory selection of all external components, the circuit is still over driven, a series resistor, rs, may be added. more specific information about on-chip oscillator design can be found in flashflex 51 oscillator circuit design con- siderations application note. figure 9-2: o scillator c haracteristics r ecommended values for crystal oscillator frequency c1 and c2 r s (optional) < 8mhz 90-110pf 100 ? 8-12mhz 18-22pf 200 ? >12mhz 18-22pf 200 ? 384 ill f12.0 xtal2 xtal1 vss c 1 using the on-chip oscillator external clock drive c 2 r s xtal2 xtal1 vss external oscillator signal nc
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 47 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 10.0 electrical specification note: this specification contains preliminary information on new products in production. the specifications are subj ect to change without notice. 10.1 operation range 10.2 reliability characteristics absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to + 150c voltage on ea# pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0 v transient voltage (<20ns) on any other pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to +6.5v maximum i ol per i/o pins p1.5, p1.6, p1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum i ol per i/o for all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ma package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5w through hole lead soldering temperature (10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. (based on package heat transfer limitations, not device power consumption. table 10-1: o perating r ange symbol description min. max unit t a ambient temperature under bias standard 0 +70 c industrial -40 +85 c v dd supply voltage 2.7 5.5 v f osc oscillator frequency for in-application programming 040mhz 0.25 40 mhz t10-1.1 384 table 10-2: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t10-2.0 384
48 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 10.3 dc electrical characteristics table 10-3: dc e lectrical c haracteristics t amb = 0c to +70c or -40c to +85c, 40mh z devices ; 4.5-5.5v; v ss = 0v symbol parameter test conditions min max units v il input low voltage 4.5 < v dd < 5.5 -0.5 0.2v dd - 0.1 v v ih input high voltage 4.5 < v dd < 5.5 0.2v dd + 0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 4.5 < v dd < 5.5 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1.5, 1.6, 1.7) v dd = 4.5v i ol = 16ma 1.0 v v ol output low voltage (ports 1, 2, 3) 1 v dd = 4.5v i ol = 100a 2 0.3 v i ol = 1.6ma 2 0.45 v i ol = 3.5ma 2 1.0 v v ol1 output low voltage (port 0, ale, psen#) 1,3 v dd = 4.5v i ol = 200a 2 0.3 v i ol = 3.2ma 2 0.45 v v oh output high voltage (ports 1, 2, 3, ale, psen#) 4 v dd = 4.5v i oh = -10a v dd - 0.3 v i oh = -30a v dd - 0.7 v i oh = -60a v dd - 1.5 v v oh1 output high voltage (port 0 in external bus mode) 4 v dd = 4.5v i oh = -200a v dd - 0.3 v i oh = -3.2ma v dd - 0.7 v v bod brown-out detection voltage 3.85 4.15 v i il logical 0 input current (ports 1, 2, 3) v in = 0.4v -1 -75 a i tl logical 1-to-0 transition current (ports 1, 2, 3) 5 v in = 2v -650 a i li input leakage current (port 0) 0.45 < v in < v dd -0.3 10 a r rst rst pulldown resistor 40 225 k ? c io pin capacitance 6 @ 1 mhz, 25c 15 pf i dd power supply current 7 in-application mode @ 20 mhz 70 ma @ 40 mhz 88 ma active mode @ 20 mhz 25 ma @ 40 mhz 45 ma idle mode @ 20 mhz 9.5 ma @ 40 mhz 20 ma standby (stop clock) mode t amb = 0c to +70c 100 a t amb = -40c to +85c 125 a power down mode minimum v dd = 2v t amb = 0c to +70c 40 a t amb = -40c to +85c 50 a t10-3.4 384
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 49 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 table 10-4: dc e lectrical c haracteristics t amb = 0c to +70c or -40c to +85c, 25mh z devices ; 2.7-3.6v; v ss = 0v symbol parameter test conditions min max units v il input low voltage 2.7 < v dd < 3.3 -0.5 0.7 v v ih input high voltage 2.7 < v dd < 3.3 0.2v dd + 0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 2.7 < v dd < 3.3 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1.5, 1.6, 1.7) v dd = 2.7v i ol = 16ma 1.0 v v ol output low voltage (ports 1, 2, 3) 1 v dd = 2.7v i ol = 100a 2 0.3 v i ol = 1.6ma 2 0.45 v i ol = 3.5ma 2 1.0 v v ol1 output low voltage (port 0, ale, psen#) 1,3 v dd = 2.7v i ol = 200a 2 0.3 v i ol = 3.2ma 2 0.45 v v oh output high voltage (ports 1, 2, 3, ale, psen#) 4 v dd = 2.7v i oh = -10a v dd - 0.3 v i oh = -30a v dd - 0.7 v i oh = -60a v dd - 1.5 v v oh1 output high voltage (port 0 in external bus mode) 4 v dd = 2.7v i oh = -200a v dd - 0.3 v i oh = -3.2ma v dd - 0.7 v v bod brown-out detection voltage 2.25 2.55 v i il logical 0 input current (ports 1, 2, 3) v in = 0.4v -1 -75 a i tl logical 1-to-0 transition current (ports 1, 2, 3) 5 v in = 2v -650 a i li input leakage current (port 0) 0.45 < v in < v dd -0.3 10 a r rst rst pulldown resistor 225 k ? c io pin capacitance 6 @ 1 mhz, 25c 15 pf i dd power supply current 7 in-application mode 70 ma active mode 22 ma idle mode 6.5 ma standby (stop clock) mode t amb = 0c to +70c 70 a t amb = -40c to +85c 88 a power down mode minimum v dd = 2v t amb = 0c to +70c 40 a t amb = -40c to +85c 50 a t10-4.4 384 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma maximum i ol per 8-bit port: 26ma maximum i ol total for all outputs: 71ma if i ol exceeds the test condition, v oh may exceed the related specification. pins ar e not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 & 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 & 3. the noise due to external bus capacitance discharging into the port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. i n the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 3. load capacitance for port 0, ale & psen#= 100pf, load capacitance for all other outputs = 80pf.
50 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 10-1: i dd t est c ondition , a ctive m ode figure 10-2: i dd t est c ondition , i dle m ode figure 10-3: i dd t est c ondition , p ower -d own m ode figure 10-4: i dd t est c ondition , s tandby (s top c lock ) m ode 4. capacitive loading on ports 0 & 2 may cause the v oh on ale and psen# to momentarily fall below the v dd - 0.7 specification when the address bits are stabilizing. 5. pins of ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when vin is approximately 2v. 6. pin capacitance is characterized but not tested. ea# is 25pf (max). 7. see figures 10-1, 10-2, 10-3 and 10- 4 for test conditions. minimum v dd for power down is 2.0v. v dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected 89x564 xtal1 384 ill f26.2 v ss i dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected xtal1 384 ill f24.2 v ss i dd 89x564 v dd v dd v dd v dd = 2v p0 ea# rst xtal2 (nc) all other pins disconnected xtal1 384 ill f25.2 v ss i dd 89x564 v dd v dd v dd v dd = 5v p0 ea# rst xtal2 (nc) all other pins disconnected xtal1 384 ill f33.2 v ss i dd 89x564
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 51 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 10.4 ac electrical characteristics ac characteristics: (over operating conditions: load capacitance for port 0, ale#, and psen# = 100pf; load capacitance for all other outputs = 80pf) table 10-5: ac e lectrical c haracteristics (1 of 2) t amb = 0c to +70c or -40c to +85c, v dd = 2.7-3.6 @25mh z , 4.5-5.5 @ 40mh z , v ss = 0 symbol parameter oscillator units 25mhz 40mhz variable min max min max min max 1/t clcl oscillator frequency 040mhz t lhll ale pulse width 65 35 2t clcl - 15 ns t avll address valid to ale low 15 t clcl - 25 (3v) ns 10 t clcl - 15 (5v) ns t llax address hold after ale low 15 t clcl - 25 (3v) ns 10 t clcl - 15 (5v) ns t lliv ale low to valid instr in 95 4t clcl - 65 (3v) ns 55 4t clcl - 45 (5v) ns t llpl ale low to psen# low 15 t clcl - 25 (3v) ns 10 t clcl - 15 (5v) ns t plph psen# pulse width 95 60 3t clcl - 25 (3v) 3t clcl - 15 (5v) ns t pliv psen# low to valid instr in 65 3t clcl - 55 (3v) ns 25 3t clcl - 50 (5v) ns t pxix input instr hold after psen# 0ns t pxiz input instr float after psen# 35 t clcl - 5 (3v) ns 10 t clcl - 15 (5v) ns t aviv address to valid instr in 120 5t clcl - 80 (3v) ns 65 5t clcl - 60 (5v) ns t plaz psen# low to address float 10 10 10 ns t rlrh rd# pulse width 200 120 6t clcl - 40 (3v) 6t clcl - 30 (5v) ns t wlwh write pulse width (we#) 200 120 6t clcl - 40 (3v) 6t clcl - 30 (5v) ns t rldv rd# low to valid data in 110 5t clcl - 90 (3v) ns 75 5t clcl - 50 (5v) ns t rhdx data hold after rd# 00 0 ns t rhdz data float after rd# 55 2t clcl - 25 (3v) ns 38 2t clcl - 12 (5v) ns t lldv ale low to valid data in 230 8t clcl - 90 (3v) ns 150 8t clcl - 50 (5v) ns t avdv address to valid data in 270 9t clcl - 90 (3v) ns 150 9t clcl - 75 (5v) ns t llwl ale low to rd# or wr# low 95 145 60 90 3t clcl - 25 (3v) 3t clcl - 15 (5v) 3t clcl + 25 (3v) 3t clcl + 15 (5v) ns t avwl address to rd# or wr# low 85 4t clcl - 75 (3v) ns 70 4t clcl - 30 (5v) ns t qvwx data valid to wr# high to low transition 00 0 ns t whqx data hold after wr# 13 t clcl - 27 (3v) ns 5t clcl - 20 (5v) ns
52 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 10.5 ac characteristics explanation of symbols each timing symbol has 5 characters. the first character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. for example: t avll = time from address valid to ale low t llpl = time from ale low to psen# low figure 10-5: ac t esting i nput /o utput , f loat w aveform t qvwh data valid to wr# high 433 7t clcl - 70 (3v) ns 125 7t clcl - 50 (5v) ns t rlaz rd# low to address float 0 0 0 ns t whlh rd# to wr# high to ale high 43 123 t clcl - 25 (3v) t clcl + 25 (3v) ns 10 40 t clcl - 15 (5v) t clcl + 15 (5v) ns t10-5.5 384 table 10-5: ac e lectrical c haracteristics (c ontinued ) (2 of 2) t amb = 0c to +70c or -40c to +85c, v dd = 2.7-3.6 @25mh z , 4.5-5.5 @ 40mh z , v ss = 0 symbol parameter oscillator units 25mhz 40mhz variable min max min max min max a: address q: output data c: clock r: rd# signal d: input data t: time h: logic level high v: valid i: instruction (program memory contents) w: wr# signal l: logic level low or ale x: no longer a valid logic level p: psen# z: high impedance (float) v lt ac inputs during testing are driven at v iht (v dd -0.5v) for logic "1" and v ilt (0.45v) for a logic "0". measurement reference points for inputs and outputs are at v ht (0.2v dd + 0.9) and v lt (0.2v dd - 0.1) for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh = 20ma. v ht v iht v ilt v load +0.1v v load -0.1v v oh -0.1v timing reference points v ol +0.1v v load 384 ill f28b.0 384 ill f28a.2 note: v ht - v high test v lt - v low test v iht -v input high test v ilt - v input low test
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 53 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 10-6: e xternal p rogram m emory r ead c ycle figure 10-7: e xternal d ata m emory r ead c ycle 384 ill f13.0 port 2 port 0 psen# ale a7 - a0 t llax t plaz t pxiz t llpl t aviv t avll t pxix t lhll t lliv t pliv t plph instr in a15 - a8 a15 - a8 a7 - a0 384 ill f14.0 port 2 port 0 rd# psen# ale t lhll p2[7:0] or a15-a8 from dph a7-a0 from ri or dpl t avdv t avwl data in instr in t rlaz t avll t llax t llwl t lldv t rlrh t rldv t rhdz t whlh t rhdx a15-a8 from pch a7-a0 from pcl
54 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 10-8: e xternal d ata m emory w rite c ycle figure 10-9: e xternal c lock d rive w aveform table 10-6: e xternal c lock d rive symbol parameter oscillator units 25mhz 40mhz variable minmaxminmax min max 1/t clcl oscillator frequency 0 40 mhz t chcx high time 0.35t clcl 0.65t clcl ns t clcx low time 0.35t clcl 0.65t clcl ns t clch rise time 20 10 ns t chcl fall time 20 10 ns t10-6.2 384 384 ill f15.0 port 2 port 0 wr# psen# ale t lhll p2[7:0] or a15-a8 from dph a7-a0 from ri or dpl data out instr in t avll t avwl t llwl t llax t qvwx t wlwh t qvwh t whqx t whlh a15-a8 from pch a7-a0 from pcl 0.2 v dd -0.1 0.45 v t chcl t clcl t clch t clcx t chcx 0.7 v dd v dd = -0.5 384 ill f30.0
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 55 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 figure 10-10: s hift r egister m ode t iming w aveforms table 10-7: s erial p ort t iming symbol parameter oscillator units 25mhz 40mhz variable min max min max min max t xlxl serial port clock cycle time 0 0.36 12t clcl ms t qvxh output data setup to clock rising edge 700 117 10t clcl - 133 ns t xhqx output data hold after clock rising edge 50 2t clcl - 117 ns 02t clcl - 50 ns t xhdx input data hold after clock rising edge 0 0 0 ns t xhdv clock rising edge to input data valid 700 117 10t clcl - 133 ns t10-7.2 384 384 ill f29.0 ale 0 instruction clock output data write to sbuf valid valid valid valid valid valid valid valid input data clear ri 01 2 34 567 t xlxl t qvxh t xhqx t xhdv t xhdx set ti set r i 1 2 3 4 5 6 7 8
56 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 11.0 product ordering information 11.1 valid combinations valid combinations for sst89e564 sst89e564-40-c-pi sst89e564-40-c-nj sst89e564-40-c-tqj sst89e564-40-i-pi sst89e564-40-i-nj sst89e564-40-i-tqj valid combinations for sst89v564 sst89v564-25-c-pi sst89v564-25-c-nj sst89v564-25-c-tqj sst89v564-25-i-pi sst89v564-25-i-nj sst89v564-25-i-tqj valid combinations for sst89e554 sst89e554-40-c-pi sst89e554-40-c-nj sst89e554-40-c-tqj sst89e554-40-i-pi sst89e554-40-i-nj sst89e554-40-i-tqj valid combinations for sst89v554 sst89v554-25-c-pi sst89v554-25-c-nj sst89v554-25-c-tqj sst89v554-25-i-pi sst89v554-25-i-nj sst89v554-25-i-tqj note: valid combinations are those products in ma ss production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combin ations. device speed suffix1 suffix2 sst89 x 5x4 -xx -x -x x package modifier i = 40 pins j = 44 pins package type p = pdip n = plcc tq = tqfp operation temperature c = commercial = 0c to +70c i = industrial = -40c to +85c operating frequency 25 = 0-25mhz 40 = 0-40mhz feature set and flash memory size 564 = c52 feature set + 64(72)* kbyte 554 = c52 feature set + 32(40)* kbyte * = 8k additional flash can be enabled voltage range e = 4.5-5.5v v = 2.7-3.6v device family 89 = c51 core
preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 57 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 12.0 packaging diagrams 40- pin p lastic d ual i n - line p ins (pdip) sst p ackage c ode : pi 44- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nj 40.pdippi-ill.7 pin #1 identifier c l 40 1 base plane seating plane .220 max. 12? 4 places .600 bsc .100 bsc .100 ? .200 .015 .022 .045 .055 .063 .090 .015 min. .065 .075 2.020 2.070 .008 .012 0? 15? .600 .625 .530 .557 note: 1. complies with jedec publication 95 ms-011 ac dimensions (except as noted), although some dimensions may be more string ent. ? = jedec min is .115; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .025 .045 .013 .021 .590 .630 .100 .112 .020 min. .165 .180 top view side view bottom view 144 .026 .032 .500 ref. 44.plcc.nj-ill.7 note: 1. complies with jedec publication 95 ms-018 ac dimensions (except as noted), although some dimensions may be more string ent. ? = jedec min is .650; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc. .050 bsc. .026 .032 .042 .056 .646 ? .656 .042 .048 .042 .048 optional pin #1 identifier .646 ? .656 .685 .695 .685 .695 .020 r. max. .147 .158 r. x45?
58 preliminary specifications flashflex51 mcu sst89e564 / sst89v564 / sst89e554 / sst89v554 ?2001 silicon storage technology, inc. s71181-03-000 9/01 384 44- lead t hin q uad f lat p ack (tqfp) sst p ackage c ode : tqj .45 .75 10.00 bsc 12.00 bsc 10.00 bsc 12.00 bsc 1.00 ref 0?- 7? 1 11 33 23 12 22 44 34 1.2 max. .95 1.05 .05 .15 pin #1 identifier .30 .45 .09 .20 .80 bsc note: 1. complies with jedec publication 95 ms-026 acb dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (0.05) mm. 4. package body dimensions do not include mold flash. maximum allowable mold flash is .25mm. 44.tqfp-tqj-ill.6 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.ssti.com

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